uvm_object & uvm_component

Everything in UVM inherits from one of two base classes. Knowing which to use is essential.

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The Class Hierarchy

text Copy
               uvm_void
                  │
             uvm_object        ← Data / transient items
            ┌─────┴──────┐
    uvm_transaction   uvm_component  ← Structural / persistent
            │          ┌────┴─────┐
   uvm_sequence_item  uvm_driver  uvm_monitor  uvm_env ...

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uvm_object — For Data Items

Use uvm_object for things that represent data or configuration:

• Sequence items (transactions)
• Configuration objects
• Register models
• Anything created, used, and discarded

systemverilog Copy
class apb_transaction extends uvm_sequence_item;
    `uvm_object_utils(apb_transaction)

    rand bit [31:0] addr;
    rand bit [31:0] data;
    rand bit        write;

    function new(string name = "apb_transaction");
        super.new(name);
    endfunction

    // Convert to human-readable string for debug
    function string convert2string();
        return $sformatf("addr=0x%08h data=0x%08h %s",
            addr, data, write ? "WR" : "RD");
    endfunction
endclass

Key characteristics of uvm_object:

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uvm_component — For Structural Elements

Use uvm_component for things that are part of the testbench structure:

• Drivers, monitors, sequencers
• Agents, environments
• Scoreboards, coverage collectors

systemverilog Copy
class apb_driver extends uvm_driver #(apb_transaction);
    `uvm_component_utils(apb_driver)

    virtual apb_if vif;

    function new(string name, uvm_component parent);
        super.new(name, parent);  // Note: takes parent!
    endfunction

    function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))
            `uvm_fatal("NOVIF", "Virtual interface not found")
    endfunction

    task run_phase(uvm_phase phase);
        // Drive signals...
    endtask
endclass

Key characteristics of uvm_component:

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The Utility Macros

Always register your classes. Without registration, the factory can't create or override them.

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Quick Decision Guide

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Field Automation (Optional)

UVM provides field macros for automatic copy(), compare(), print(), pack():

systemverilog Copy
class my_txn extends uvm_sequence_item;
    `uvm_object_utils_begin(my_txn)
        `uvm_field_int(addr, UVM_ALL_ON)
        `uvm_field_int(data, UVM_ALL_ON)
        `uvm_field_enum(op_t, op, UVM_ALL_ON)
    `uvm_object_utils_end

    rand bit [31:0] addr;
    rand bit [31:0] data;
    rand op_t       op;

    function new(string name = "my_txn");
        super.new(name);
    endfunction
endclass

Now you can do:

systemverilog Copy
my_txn a, b;
a = my_txn::type_id::create("a");
a.randomize();

// Clone
b = my_txn::type_id::create("b");
b.copy(a);

// Compare
if (!a.compare(b))
    `uvm_error("CMP", "Mismatch!")

// Print
a.print();

Performance note: Field macros add overhead. In high-performance simulations, implement do_copy() and do_compare() manually.